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HC-5502B1
April 1999 File Number 4127.2
SLIC Subscriber Line Interface Circuit [ /Title (HC5502B 1) /Subject (SLIC Subscriber Line Interface Circuit) /Autho r () /Keywords (Intersil Semiconductor, RSLIC 18, Telecom, SLICs, SLACs , Telephone, Telephony, WLL, Wireless Local Loop, PBX, Private Branch Exchan ge,
The Intersil SLIC incorporates many of the BORSHT function on a single IC chip. This includes DC battery feed, a ring relay driver, supervisory and hybrid functions. This device is designed to maintain transmission performance in the presence of externally induced longitudinal currents. Using the unique Intersil dielectric isolation process, the SLIC can operate directly with a wide range of station battery voltages. The SLIC also provides selective denial of power. If the PBX system becomes overloaded during an emergency, the SLIC will provide system protection by denying power to selected subscriber loops. The Intersil SLIC is ideally suited for the design of new digital PBX systems, by eliminating bulky hybrid transformers.
Features
* Low Cost Version of HC-5502B * Capable of 12V or 5V (VB+) Operation * Monolithic Integrated Device * DI High Voltage Process * Compatible With Worldwide PBX Performance Requirements * Controlled Supply of Battery Feed Current for Short Loops (30mA) * Internal Ring Relay Driver * Low Power Consumption During Standby * Switch Hook, Ground Key and Ring Trip Detection Functions * Selective Denial of Power to Subscriber Loops
Ordering Information
PART NUMBER HC3-5502B1-5 HC4P5502B1-5 HC9P5502B1-5 TEMP. RANGE (oC) 0 to 75 0 to 75 0 to 75 PACKAGE 24 Ld PDIP 28 Ld PLCC 24 Ld SOIC PKG. NO. E24.6 N28.45 M24.3
Applications
* Solid State Line Interface Circuit for Analog and Digital PBX Systems * Direct Inward Dial (DID) Trunks * Voice Messaging PBXs * Related Literature - AN549, The HC-5502S/4X Telephone Subscriber Line Interface Circuits (SLIC) - AN571, Using Ring Sync with HC-5502A and HC-5504 SLICs
Pinouts
HC-5502B1 (PDIP, SOIC) TOP VIEW
TIP RING VB + C1 (NOTE) C3 DG RS RD TF 1 2 3 4 5 6 7 8 9 24 TX 23 AG 22 C4 21 RX 20 +IN 19 -IN 18 OUT 17 C2 16 RC 15 PD 14 GKD 13 SHD 12 13 RF VB 14 15 16 17 18 BG N/C SHD GKD PD C1 (NOTE) C3 DG N/C RS 5 6 7 8 9 25 RX 24 +IN 23 -IN 22 N/C 21 OUT 20 C2 19 RC
HC-5502B1 (PLCC) TOP VIEW
VB+ RING N/C TIP AG C4 TX
4
3
2
1
28 27 26
RF 10 VB- 11 BG 12
RD 10 TF 11
NOTE: Optional.
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-724-7143| Copyright (c) Intersil Corporation 1999
HC-5502B1
Absolute Maximum Ratings (Note 1)
Supply Voltage (VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -60 to 0.5V (VB+) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V (VB+ - VB-) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75V Relay Drive Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . -0.5 to 15V
Thermal Information
Thermal Resistance (Typical, Note 2) JA (oC/W) 24 Lead PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 28 Lead PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Maximum Junction Temperature Plastic . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC (SOIC and PLCC - Lead Tips Only)
Operating Conditions
Relay Driver Voltage (VRD) . . . . . . . . . . . . . . . . . . . . . . . . 5V to 12V Positive Supply Voltage (VB+) . . . 4.75V to 5.25V or 10.8V to 13.2V Negative Supply Voltage (VB-). . . . . . . . . . . . . . . . . . . .-42V to -58V High Level Logic Input Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . 2.4V Low Level Logic Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 0.6V Loop Resistance (RL) . . . . . . . . . . . . . . . . . . . . . . . . . 200 to 1200 Operating Temperature Range HC-5502B1-5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 75oC
Die Characteristics
Transistor Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 Diode Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Die Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137 x 102 mils Substrate Potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VBProcess . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Bipolar-DI
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES: 1. Absolute maximum ratings are limiting values, applied individually, beyond which the serviceability of the circuit may be impaired. Functional operability under any of these conditions is not necessarily implied. 2. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
PARAMETER On Hook Power Dissipation Off Hook Power Dissipation Off Hook IB+ Off Hook IB+x Off Hook IBOff Hook Loop Current Off Hook Loop Current Off Hook Loop Current Fault Currents TIP to Ground RING to Ground TIP to RING TIP and RING to Ground Ring Relay Drive VOL Ring Relay Driver Off Leakage Ring Trip Detection Period Switch Hook Detection Threshold
Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range CONDITIONS ILONG = 0 (Note 4), VB+ = 12V RL = 600, ILONG = 0 (Note 4), VB+ = 12V RL = 600, ILONG = 0 (Note 4), TA = -40oC RL = 600, ILONG = 0 (Note 4), TA = 25oC RL = 600, ILONG = 0 (Note 4) RL = 1200, ILONG = 0 (Note 4) RL = 1200, VB- = -42V, ILONG = 0 (Note 4), TA = 25oC RL = 200, ILONG = 0 (Note 4) MIN 17.5 25.5 TYP 135 450 21 30 MAX 235 690 6.0 5.3 39 34.5 UNITS mW mW mA mA mA mA mA mA
IOL = 62mA VRD = 12V, RC = 1 = HIGH, TA = 25oC RL = 600, TA = 25oC SHD = VOL SHD = VOH 10 20 0
14 47 30 47 0.2 2 2 -
0.5 100 3 5 10 5
mA mA mA mA V A Ring Cycles mA mA mA mA mA ms
Ground Key Detection Threshold
GKD = VOL GKD = VOH
Loop Current During Power Denial Dial Pulse Distortion
RL = 200
4-2
HC-5502B1
Electrical Specifications
PARAMETER Receive Input Impedance Transmit Output Impedance Two Wire Return Loss SRL LO ERL SRL HI Longitudinal Balance 2-Wire Off Hook 2-Wire On Hook 4-Wire Off Hook Low Frequency Longitudinal Balance R.E.A. Method, (Note 3) RL = 600, 0oC TA 75oC At 1kHz, 0dBm Input Level, Referenced 600 200 - 3400Hz Referenced to Absolute Loss at 1kHz and 0dBm Signal Level (Note 3) (Note 3) 1VRMS 200Hz - 3400Hz, (Note 3) IEEE Method 0oC TA 75oC 53 53 50 (Note 3) Balance Network Set Up for 600 Termination at 1kHz VB+ = 5V VB+ = 12V At 1kHz, (Note 3) Referenced to 0dBm Level +3 to -40dBm -40 to -50dBm -50 to -55dBm Power Supply Rejection Ratio VB+ to 2-Wire VB+ to Transmit VB- to 2-Wire VB- to Transmit VB+ to 2-Wire VB+ to Transmit VB- to 2-Wire VB- to Transmit Logic Input Current (RS, RC, PD) 0V VIN 5V 200 - 16kHz RL = 600 (Note 3) 30 - 60Hz RL = 600 0.05 0.1 0.3 dB dB dB 30 1.5 1.75 58 58 58 0.05 0.02 1 -89 40 23 -67 0.2 0.05 5 -85 2 dB dB dB dBrnC dBm0p dB dB dBrnC dBm0p s dB VPEAK VPEAK (Note 3) (Note 3) Referenced to 600 +2.16F (Note 3) Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS MIN TYP 110 10 MAX 20 UNITS k
-
15.5 24 31
-
dB dB dB
Insertion Loss 2-Wire to 4-Wire, 4-Wire to 2-Wire Frequency Response Idle Channel Noise 2-Wire to 4-Wire, 4-Wire to 2-Wire Absolute Delay 2-Wire to 4-Wire, 4-Wire to 2-Wire Trans Hybrid Loss Overload Level 2-Wire to 4-Wire, 4-Wire to 2-Wire Level Linearity 2-Wire to 4-Wire, 4-Wire to 2-Wire
15 15 15 15 30 30 30 30 -
-
100
dB dB dB dB dB dB dB dB A
4-3
HC-5502B1
Electrical Specifications
PARAMETER Logic Inputs Logic `0' VIL Logic `1' VIH Logic Outputs Logic `0' VOL Logic `1' VOH ILOAD 800A, VB+ = 12V, 5V ILOAD 80A, VB+ = 12V ILOAD 40A, VB+ = 5V 2.7 2.7 0.1 5.0 0.5 5.5 5.0 V V V 2.0 0.8 5.5 V V Unless Otherwise Specified, VB- = -48V, VB+ = 12V and 5V, AG = BG = DG = 0V, Typical Parameters TA = 25oC. Min-Max Parameters are Over Operating Temperature Range (Continued) CONDITIONS MIN TYP MAX UNITS
Uncommitted Op Amp Specifications
PARAMETER Input Offset Voltage Input Offset Current Input Bias Current Differential Input Resistance Output Voltage Swing (Note 3) RL = 10k, VB+ = 12V RL = 10k, VB+ = 5V Output Resistance Small Signal GBW NOTES: 3. These parameters are controlled by design or process parameters and are not directly tested. These parameters are characterized upon initial design release, upon design changes which would affect these characteristics, and at intervals to assure product quality and specification compliance. 4. ILONG = Longitudinal Current. AVCL = 1 (Note 3) (Note 3) CONDITIONS MIN TYP 5 10 20 1 6.2 3 10 1 MAX 6.6 UNITS mV nA nA M VPEAK VPEAK MHz
4-4
HC-5502B1 Pin Descriptions
28 PIN PLCC 2 24 PIN DIP/SOIC 1 SYMBOL TIP DESCRIPTION An analog input connected to the TIP (more positive) side of the subscriber loop through a 150 feed resistor and a ring relay contact. Functions with the Ring terminal to receive voice signals from the telephone and for loop monitoring process. An analog input connected to the RING (more negative) side of the subscriber loop through a 150 feed resistor and a ring relay contact. Functions with the Tip terminal to receive voice signals from the telephone and for loop monitoring purposes. Positive Voltage Source - Most positive supply. VB+ is typically 12V or 5V. Capacitor #1 - Optional Capacitor used to improve power supply rejection. This pin should be left open if unused. Capacitor #3 - An external capacitor to be connected between this terminal and analog ground. Required for proper operation of the loop current limiting function, and for filtering VB- supply. Typical value is 0.3F, 30V. Digital Ground - To be connected to zero potential and serves as a reference for all digital inputs and outputs on the SLIC. Ring Synchronization Input - A TTL - Compatible Clock Input. The clock should be arranged such that a positive transition occurs on the negative going zero crossing of the ring voltage source, ensuring that the ring relay is activated and deactivated when the instantaneous ring voltage is near zero. If synchronization is not required, tie to 5V. Relay Driver - A low active open collector logic output. When enabled, the external ring relay is energized. Tip Feed - A low impedance analog output connected to the TIP terminal through a 150 feed resistor. Functions with the RF terminal to provide loop current, feed voice signals to the telephone set, and sink longitudinal current. Ring Feed - A low impedance analog output connected to the RING terminal through a 150 feed resistor. Functions with the TF terminal to provide loop current, feed voice signal to the telephone set, and sink longitudinal current. Negative Voltage Source - Most negative supply. VB- is typically -48V with an operational range of -42V to -58V. Frequently referred to as "battery". Battery Ground - To be connected to zero potential. All loop current and some quiescent current flows into this ground terminal. Switch Hook Detection - A Low Active LS TTL - Compatible Logic Output. This output is enabled for loop currents exceeding 10mA and disabled for loop currents less than 5mA. Ground Key Detection - A Low Active LS TTL - Compatible Logic Output. This output is enabled if the DC current into the ring lead exceeds the DC current out of the tip lead by more than 20mA, and disabled if this current difference is less than 10mA. Power Denial - A Low Active TTL - Compatible Logic Input. When enabled the switch hook detect (SHD) and ground key detect (GKD) are not necessarily valid, and the relay driver (RD) output is disabled. Ring Command - A Low Active TTL - Compatible Logic Input. When enabled, the relay driver (RD) output goes low on the next rising edge of the ring sync (RS) input, as long as the SLIC is not in the power denial state (PD = 0) or the subscriber is not already off- hook (SHD = 0). Capacitor #2 - An external capacitor to be connected between this terminal and digital ground. Prevents false ground key indications from occurring during ring trip detection. Typical value is 0.15F, 10V. This capacitor is not used if ground key function is not required. The analog output of the spare operational amplifier. The inverting analog input of the spare operational amplifier. The non-inverting analog input of the spare operational amplifier. Receive Input, Four Wire Side - A high impedance analog input which is internally biased. Capacitive coupling to this input is required. AC signals appearing at this input differentially drive the Tip feed and Ring feed amplifiers, which in turn drive tip and ring through 300 of feed resistance on each side of the line.
3
2
RING
4 5 6
3 4 5
VB+ C1 C3
7 9
6 7
DG RS
10 11
8 9
RD TF
12
10
RF
13 14 16 17
11 12 13 14
VBBG SHD GKD
18 19
15 16
PD RC
20
17
C2
21 23 24 25
18 19 20 21
OUT -IN +IN RX
4-5
HC-5502B1 Pin Descriptions
28 PIN PLCC 26 24 PIN DIP/SOIC 22 (Continued) SYMBOL C4 DESCRIPTION Capacitor #4 - An external capacitor to be connected between this terminal and analog ground. This capacitor prevents false ground key indication and false ring trip detection from occurring when longitudinal currents are induced onto the subscriber loop from nearby power lines and other noise sources. This capacitor is also required for the proper operation of ring trip detection. Typical value is 0.5F to 1.0F, 20V. This capacitor should be nonpolarized. Analog Ground - To be connected to zero potential and serves as a reference for the transmit output (TX) and receive input (RX) terminals. Transmit Output, Four Wire Side - A low impedance analog output which represents the differential voltage across Tip and Ring. Transhybrid balancing must be performed (using the SLIC microcircuit's spare op amp) beyond this output to completely implement two to four wire conversion. This output is unbalanced and referenced to analog ground. Since the DC level of this output varies with loop current, capacitive coupling to the next stage is essential. No Internal Connection.
27 28
23 24
AG TX
1, 8, 5, 22 NOTE:
NC
5. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
Functional Diagram
RING VOLTAGE
RING SYNC
RS RC RD RING CONTROL
RING TRIP LOOP MONITORING
SHD SWITCH HOOK DETECTION GKD GROUND KEY DETECTION
RING COMMAND
TIP
RING RELAY 150
TIP DIFF AMP + TX TRANSMIT OUTPUT
150 2-WIRE LOOP SECONDARY PROTECTION BG VB RF 150 RING RING 150 POWER DENIAL PD SLIC MICROCIRCUIT -1 LOOP CURRENT LIMITER TF VB BATTERY FEED +1
OUT +IN
+ LINE DRIVERS OP AMP
-IN RX RECEIVE INPUT
4-6
HC-5502B1 Schematic
SLIC FUNCTIONAL SCHEMATIC PIN NUMBERS FOR DIP/SOIC PACKAGE
21 RCV 22 C4 11 VBAT 12 BAT GND 23 6 3 VB + 4 C1 20 + 19 18 VB + OUT
ANA DIG GND VB+ GND
+
VOLTAGE AND CURRENT BIAS NETWORK VB + 1 TF VBAT IB4 1 TIP R7 R8 R10 R11 R9 R3 2 RING R4 R1 R2 R16 R15 IB6 A-100 TRANSV'L I/VAMP VBAT R6 VBAT/2 REFERENCE VB2 A-300 RING FEED AMP VBAT R14 R21 R18 QD27 VBAT VB + VBAT R5 VB + VB + QD3 QD36 A-200 LONG'L I/V AMP IB7 R12 VB+ R20 + VBAT VBAT IB8 VB4 RING TRIP DETECTOR 5V A-400 TIP FEED AMP + R17 VB2 IB1 IB2 IB3 IB4 IB5 IB6 IB7 IB8 VBAT IB9 IB10 IB11
VB1 VB2 VB3 VB4 VB5 -5V
A-500 OP AMP
VBAT IB3
-5V IB10 VB+
GK GND SHORTS CURRENT LIMITING IB1
GKD 14
SWITCH HOOK DETECTOR VB + + IB9 QD28 THERMAL LIMITING VB5 VB1
+ VB3 VBAT IIL LOGIC INTERFACE SH C2 17
SHD 13
-
RC 16
10 RF
LOOP CURRENT LIMITING IB2 VB5 +
PD RFC
15
IB5
R19 VBAT R13 VBAT VBAT
C3 5
TX 24
RS 7
RD 8
4-7
HC-5502B1 Logic Diagram
LOGIC GATE SCHEMATIC
C2
GK
1
2
LOGIC BIAS DELAY 6 4 8 3
5 7 9 12
SH
16 10 13
11 15 TTL TO STTL TO R21
14
RELAY DRIVER
TTL TO STTL
TTL TO STTL
C B A B A
STTL TO TTL
STTL TO TTL
RS
RC
PD
C SCHOTTKY LOGIC
RD
SHD
GKD
Overvoltage Protection and Longitudinal Current Protection
The SLIC device, in conjunction with an external protection bridge, will withstand high voltage lightning surges and power line crosses. High voltage surge conditions are as specified in Table 1. The SLIC will withstand longitudinal currents up to a maximum or 30mARMS, 15mARMS per leg, without any performance degradation.
PARAMETER Longitudinal Surge Metallic Surge T/GND R/GND 50/60Hz Current T/GND R/GND
TABLE 1. TEST CONDITION 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall 10s Rise/ 1000s Fall 11 Cycles Limited to 10ARMS PERFORMANCE (MAX) 1000 (Plastic) 1000 (Plastic) 1000 (Plastic) 700 (Plastic) UNITS VPEAK VPEAK VPEAK VRMS
4-8
HC-5502B1 Applications Diagram
SYSTEM CONTROLLER
Z1 15
PTC RING GENERATOR 150V PEAK (MAX)
12V
13
14
7
16 BALANCE NETWORK 21 24 C6 R1 R2 C5 C7 ZB R3 PCM FILTER/ CODEC SWITCHING NETWORK
RING RELAY RB1 CS RS RB2
POWER SWITCH GROUND RING RING DENIAL HOOK KEY SYNC CMD 8 DETECT DETECT RD RECEIVE TRANSMIT 1 9 TIP FEED SLIC HC-5502B1 OP AMP
TIP
TIP
+IN -IN OUT C1
20 19 18 4 17 5 22
SUBSCRIBER LOOP
PRIMARY PROTECTION
(N
TE O
8)
VB -
10 2
RING FEED RING NEG. BATT. 11 C8 -48V BATT. GND. 12 DIG. ANA. GND. GND. 6 23 C9
C2 C3 C4 POS. SUPP. 3
RB4 RING RB3
C4 C3 C2 C1
PIN NUMBERS GIVEN FOR DIP/SOIC PACKAGE.
VB+
FIGURE 1. TYPICAL LINE CIRCUIT APPLICATION WITH THE MONOLITHIC SLIC
Typical Component Values
C1 = 0.5F (Note 6). C2 = 0.15F, 10V. C3 = 0.3F, 30V. C4 = 0.5F to 1.0F, 10%, 20V (Should be nonpolarized). C5 = 0.5F, 20V. C6 = C7 = 0.5F (10% Match Required) (Note 7), 20V. C8 = 0.01F, 100V. C9 = 0.01F, 20V, 20%.
NOTES: 6. C1 is an optional capacitor used to improve VB+ supply rejection. This pin must be left open if unused. 7. To obtain the specified transhybrid loss it is necessary for the three legs of the balance network, C6-R1 and R2 and C7-ZB-R3, to match in impedance to within 0.3%. Thus, if C6 and C7 are 1F each, a 20% match is adequate. It should be noted that the transmit output to C6 sees a -22V step when the loop is closed. Too large a value for C6 may produce an excessively long transient at the op amp output to the PCM Filter/CODEC. 8. A 0.5F and 100k gives a time constant of 50ms. The uncommitted op amp output is internally clamped to stay within 6.6V and is current limited. 9. Secondary protection diode bridge recommended is a 2A, 200V type. 10. All grounds (AG, BG, and DG) must be applied before VB+ or VB-. Failure to do so may result in premature failure of the part. If a user wishes to run separate grounds off a line card, the AG must be applied first.
R1 = R2 = R3 = 100k (0.1% Match Required, 1% absolute value), ZB = 0 for 600 Terminations (Note 7). RB1 = RB2 = RB3 = RB4 = 150 (0.1% Match Required, 1% absolute value). RS = 1k, CS = 0.1F, 200V typically, depending on VRING and line length. Z1 = 150V to 200V transient protection. PTC used as ring generator ballast.
4-9
HC-5502B1 Dual-In-Line Plastic Packages (PDIP)
N E1 INDEX AREA 12 3 N/2 -B-AD BASE PLANE SEATING PLANE D1 B1 B 0.010 (0.25) M D1 A1 A2 L A C L E
E24.6 (JEDEC MS-011-AA ISSUE B)
24 LEAD DUAL-IN-LINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 B B1 C D D1 E eA eC
C A BS C
MILLIMETERS MIN 0.39 3.18 0.356 0.77 0.204 29.3 0.13 15.24 12.32 MAX 6.35 4.95 0.558 1.77 0.381 32.7 15.87 14.73 NOTES 4 4 8 5 5 6 5 6 7 4 9 Rev. 0 12/93
MIN 0.015 0.125 0.014 0.030 0.008 1.150 0.005 0.600 0.485
MAX 0.250 0.195 0.022 0.070 0.015 1.290 0.625 0.580
-C-
e
eB
NOTES: 1. Controlling Dimensions: INCH. In case of conflict between English and Metric dimensions, the inch dimensions control. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication No. 95. 4. Dimensions A, A1 and L are measured with the package seated in JEDEC seating plane gauge GS-3. 5. D, D1, and E1 dimensions do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.010 inch (0.25mm). 6. E and eA are measured with the leads constrained to be perpendicular to datum -C- . 7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater. 8. B1 maximum dimensions do not include dambar protrusions. Dambar protrusions shall not exceed 0.010 inch (0.25mm). 9. N is the maximum number of terminal positions. 10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3, E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
E1 e eA eB L N
0.100 BSC 0.600 BSC 0.115 24 0.700 0.200
2.54 BSC 15.24 BSC 2.93 24 17.78 5.08
4-10
HC-5502B1 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP
N28.45 (JEDEC MS-018AB ISSUE A)
0.004 (0.10) C
28 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.485 0.450 0.191 0.485 0.450 0.191 28 MAX 0.180 0.120 0.495 0.456 0.219 0.495 0.456 0.219 MILLIMETERS MIN 4.20 2.29 12.32 11.43 4.86 12.32 11.43 4.86 28 MAX 4.57 3.04 12.57 11.58 5.56 12.57 11.58 5.56 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L E1 E D2/E2 VIEW "A"
D D1 D2 E E1 E2 N
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN
0.025 (0.64) MIN VIEW "A" TYP.
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
4-11
HC-5502B1 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M24.3 (JEDEC MS-013-AD ISSUE C) 24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INCHES SYMBOL A
L
MILLIMETERS MIN 2.35 0.10 0.33 0.23 15.20 7.40 MAX 2.65 0.30 0.51 0.32 15.60 7.60 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0926 0.0040 0.013 0.0091 0.5985 0.2914
MAX 0.1043 0.0118 0.020 0.0125 0.6141 0.2992
A1 B C D E
A1 0.10(0.004) C
e H h L N
0.05 BSC 0.394 0.010 0.016 24 0o 8o 0.419 0.029 0.050
1.27 BSC 10.00 0.25 0.40 24 0o 10.65 0.75 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch) 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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